74ACT74PC |
RFQ for 74ACT74PC Required Field |
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| Technical/Catalog Information | 74ACT74PC |
| Vendor | Fairchild Semiconductor |
| Category | Integrated Circuits (ICs) |
| Mounting Type | Through Hole |
| Package / Case | 14-DIP |
| Function | Set and Reset |
| Number of Bits per Element | 1 |
| Number of Elements | 2 - Dual |
| Current - Output High, Low | 24mA, 24mA |
| Output Type | Differential |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Packaging | Tube |
| Operating Temperature | -40°C ~ 85°C |
| Delay Time - Propagation | 7.5ns |
| Frequency - Clock | 210MHz |
| Voltage - Supply | 4.5 V ~ 5.5 V |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | 74ACT74PC 74ACT74PC |
| Product | Manufacturers | Pack | D/C |
| 74ACT74PC | - | 99 | 13 |
The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the
Clock Pulse input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
Features |
| ICC reduced by 50%Output source/sink 24 mAACT74 has TTL-compatible inputs |
